Compaq AlphaServer ES40 Technické informace stáhnout pdf (Strana 380)

D-22 Compaq AlphaServer ES40 Service Guide

Table D–8 I_CTL Register Fields (Continued)

Name Extent Type Description

SPE[2:0] [5:3] RW,0 Super Page Mode Enable.

Identical to the SPE bits in the Mbox

M_CTL SPE[2:0].

IC_EN[1:0] [2:1] RW,3

Icache Set Enable.

At least one set must be enabled. The entire

cache may be enabled by setting both bits.

Zero, one, or two Icache sets can be enabled.

This bit does not clear the Icache, but only

disables fills to the affected set.

SPCE [0] RW,0 System Performance Counting Enable.

Enables performance counting for the entire

system if individual counters (PCTR0 or

PCTR1) are enabled by setting PCT0_EN or

PCT1_EN, respectively.

Performance counting for individual

processes can be enabled by setting

PCTX[PPCE].

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